;lcd kunio.h  (CPU:8MHz)
;**** includes **** 
.include "m88pdef.inc"

; Load immediate word into the resister pair.
;	ldiw	Z(X,Y),var
.macro	ldiw
	ldi	@0L,low(@1)
	ldi	@0H,high(@1)
.endm
; Output immediate   outi	port,var
.macro	outi
	ldi	r16,@1
	out	@0,r16
.endm
.MACRO cpi16	;cpi16	ra,rb,0xHHHH	;ra:rb-0xHHHH	set flags:N,C,Z
	push	@0
	push	@1
	subi	@1,low(@2)
	sbci	@0,high(@2)
	pop	@1
	pop	@0
.ENDMACRO
.macro	stsi
	ldi	r16,@1
	sts	@0,r16
.endm
.MACRO addi16	;addi16	ra,rb,0xHHHH
        subi	@1,low(-@2)
        sbci	@0,high(-@2)
.ENDMACRO
;*****************************
;* レジスタ変数　設定 *
;*****************************
.def	mem_l	= r10
.def	mem_h	= r11
.def	mem_p0	= r12
.def	temp1	= r16
.def	temp2	= r17
.def	temp3	= r18
.def	temp4	= r19


;*****************************
;*　 ビット　設定　　*

;**  PORTB  ***
.equ	lcd_cs= 0
.equ	lcd_rs= 1	
;.equ	= 2	;SS
;.equ	= 3	;MOSI  lcd_SDI
;.equ	= 4	;MISO
;.equ	= 5	;SCK  lcd_SCLK
;.equ	= 6
;.equ	= 7	
;**  PORTD  **
;.equ	= 0
;.equ	= 1 
;.equ	= 2
;.equ	= 3
;.equ   = 4	
;.equ	= 5
;.equ	= 6		
;.equ	= 7
;**  PORTC  ***
;.equ	= 0
;.equ	= 1 
;.equ	= 2
;.equ	= 3
.equ	sda= 4	
.equ	scl= 5
;.equ	= 6		

.dseg
dram:	.byte 60
kp_dat:	.byte 18		
m_dat:	.byte 20
.cseg
;*********************
;* 割込みベクター *
;*********************
	rjmp start ;各種ﾘｾｯﾄ
	reti	;RJMP EXT_INT0 ;外部割り込み要求0
	reti	;EXT_INT1   ;外部割り込み要求1
	reti	;TIM2_COMP  ;ﾀｲﾏ/ｶｳﾝﾀ2 比較一致
	reti	;TIM2_OVF   ;ﾀｲﾏ/ｶｳﾝﾀ2 ｵｰﾊﾞｰﾌﾛｰ
	reti	;TIM1_CAPT   ;ﾀｲﾏ/ｶｳﾝﾀ1 ｷｬﾌﾟﾁｬ発生 mp3_dreq L→H sleep mood end
	reti	;TIM1_COMPA ;ﾀｲﾏ/ｶｳﾝﾀ1 比較A 一致
	reti	;TIM1_COMPB ;ﾀｲﾏ/ｶｳﾝﾀ1 比較B 一致
	reti	;TIM1_OVF    ;ﾀｲﾏ/ｶｳﾝﾀ1 ｵｰﾊﾞｰﾌﾛｰ
	reti	;TIM0_OVF    ;ﾀｲﾏ/ｶｳﾝﾀ0 ｵｰﾊﾞｰﾌﾛｰ
	reti	;SPI_STC    ;SPI 転送完了
	reti	;USART_RXC  ;USART 受信完了
	reti	;USART_DRE  ;USART 送信ﾊﾞｯﾌｧ空
	reti	;USART_TXC  ;USART 送信完了
	reti	;ADC_E      ;ADC 変換完了
	reti	;EE_RDY     ;EEPROM 操作可 
	reti	; ANA_COMP ;ｱﾅﾛｸﾞ ｺﾝﾊﾟﾚｰﾀ出力遷移
	reti	;TWSI ;2 線式ｼﾘｱﾙ ｲﾝﾀｰﾌｪｰｽ状態変化
	reti	;SPM_RDY ;SPM 命令操作可
;*********************
;* メイン プログラム *
;*********************
start:
	ldi	temp1,low(RAMEND)
	out	SPL,temp1
	ldi	temp1,high(RAMEND)
	out	SPH,temp1	;init Stack Pointer 
	ldi	r16,0x80	;set cpu clk 8MHz
	sts	CLKPR,r16
	ldi	r16,0x00	;1		
	sts	CLKPR,r16

	ldi	temp1,0b11010101
	out	PORTB,temp1	
	ldi	temp1,0b00101011
	out	DDRB,temp1	
	ldi	temp1,0b11111111	
	out	PORTC,temp1
	ldi	temp1,0b00110000
	out	DDRC,temp1	 
	ldi	temp1,0b11111100	
	out	PORTD,temp1
	ldi	temp1,0b00000010
	out	DDRD,temp1	


USATR_int:
	stsi	UBRR0H,0		
	stsi	UBRR0L,51		;8MHz/[(51+1)x16]-->9600Hz
	stsi	UCSR0A,1<<U2X0	;9600x2-->19200Hz
	stsi	UCSR0B,(1<<RXEN0)|(1<<TXEN0);RXEN0：受信許可、TXEN0：送信許可
	stsi	UCSR0C,(1<<UCSZ01)|(1<<UCSZ00);ビット長８bit、ストップビット１bit、非同期動作

spi_mode_set:
	outi	SPCR,0x50	;SPI master,CPOL0,CPHA=0
	outi	SPSR,0x01	;CK=8M/4=2M

	rcall lcd_int
	ldi temp1,0xb0-1
	mov r5,temp1
moji_in:
	ldi temp2,22
	clr	temp3
	ldiw z,m_dat
m_i1:
	rcall rx
	st	z+,temp1
	cpi temp1,10	;LF
	breq	m_i2
	dec temp2
	brne m_i1
m_i2:


	cbi	PORTB,lcd_cs
t2:
	cbi	PORTB,lcd_rs
	inc r5
	mov	temp1,r5 //page address 
	rcall	spi_out
	ldi temp1,0x10 //column address 0
	rcall	spi_out
	ldi temp1,0x00 //column address 0
	rcall	spi_out
	sbi	PORTB,lcd_rs

	ldi	temp1,11
	mov	r2,temp1
	ldiw	y,dram
	ldiw	x,m_dat
t3:
	ld temp1,x+
	cpi temp1,13
	breq t61
	
	rcall moji
	ldiw	z,kp_dat
	ldi r22,18
t4:
	ld temp1,z+
	cpi	r22,7
	brmi t5
	rcall	spi_out
	rjmp t6
t5:
	st y+,temp1
t6:
	dec r22
	brne t4
	clr temp1
	rcall	spi_out
	dec r2
	brne t3

t61:
	cbi	PORTB,lcd_rs
	inc r5
	mov	temp1,r5 //page address 
	rcall	spi_out
	ldi temp1,0x10 //column address 0
	rcall	spi_out
	ldi temp1,0x00 //column address 0
	rcall	spi_out

	subi  yl,low(dram)
	sbci  yh,high(dram)
	mov	temp3,yl
	ldiw	y,dram
	ldi temp4,6
	sbi	PORTB,lcd_rs
t7:
	ld temp2,y+
	mov temp1,temp2
	swap temp1
	andi temp1,0x0f
	rcall	spi_out
	mov temp1,temp2
	andi temp1,0x0f
	rcall	spi_out
	dec temp4
	brne t8
	clr temp1
	rcall	spi_out
	ldi temp4,6
t8:
	dec temp3
	brne t7

	ldi temp1,5
	cp temp1,r5
	breq t99
	rjmp moji_in
t99:
	sbi	PORTB,lcd_cs	
end:
	rjmp	moji_in
;**********************************************
moji:
	clr mem_h
	clr mem_l
	clr mem_p0

mo0:
	cpi temp1,0x21
	brcc mo1
	rjmp mo_sp
mo1:
	cpi temp1,0x80
	brcs mo_ha
	cpi temp1,0xA0
	brcs mo2	;全角文字
	cpi temp1,0xe0
	brcc mo2	;全角文字
mo_ha:	;半角→全角テーブル読込　0x25D4-0x2753
	subi temp1,0x20
	clr	 temp2
	lsl temp1
	rol temp2
	mov mem_l,temp1
	mov mem_h,temp2
	ldi temp1,0xD4
	ldi temp2,0x25
	add mem_l,temp1
	adc mem_h,temp2
	rcall mem_r0 ;2byte
	ldiw z,kp_dat
	ld	mem_h,z+
	ld	mem_l,z
	rjmp mo_en
mo2:
	ld temp2,x+
	cpi16 temp1,temp2,0x97b2
	brcs mo3
	inc mem_p0
	inc mem_p0
mo3:
	mov mem_l,temp2
	mov mem_h,temp1
	cpi temp1,0x87
	brcs mo81
	breq mo87
	cpi temp1,0x88
	breq mo88
	cpi temp1,0xa0
	brcs mo89
moe0:
	cpi	temp2,0x40
	brcs mo_sp
	ldi temp2,0x40
	ldi temp1,0xe0
	rcall ad_cal

	ldi temp2,0x98
	ldi temp1,0x6f
	add mem_l,temp2
	adc mem_h,temp1
	rjmp mo_en
mo81:
	cpi	temp2,0x40
	brcs mo_sp
	cpi16 temp1,temp2,0x83e0 ;半角→全角変換テーブル
	brcs mo82				 ;は読まない
	cpi16 temp1,temp2,0x83f6
	brcs mo_sp
mo82:
	ldi temp2,0x40
	ldi temp1,0x81
	rcall ad_cal
;	mov mem_l,temp2
;	mov mem_h,temp1
	rjmp mo_en
mo87:
	cpi	temp2,0x40
	brcs mo_sp
	ldi temp2,0x40
	sub mem_l,temp2
	clr mem_h
	rcall ad_cal1
	ldi temp2,0xcc
	ldi temp1,0x30
	add mem_l,temp2
	adc mem_h,temp1
	rjmp mo_en	
mo88:
	cpi	temp2,0x9f
	brcs mo_sp
	ldi temp2,0x9F
	sub mem_l,temp2
	clr mem_h
	rcall ad_cal1
	ldi temp2,0x56
	ldi temp1,0x37
	add mem_l,temp2
	adc mem_h,temp1
	rjmp mo_en
mo89:
	cpi	temp2,0x40
	brcs mo_sp
	ldi temp2,0x40
	ldi temp1,0x89
	rcall ad_cal
	ldi temp2,0xf2
	ldi temp1,0x3d
	add mem_l,temp2
	adc mem_h,temp1
	rjmp mo_en
mo_sp:
	clr mem_p0
mo_en:
	rcall mem_r
	ret

ad_cal:
	sub mem_l,temp2
 	sub mem_h,temp1   
	ldi temp1,189
	mul temp1,mem_h
	clr mem_h
	add mem_l,r0
	adc mem_h,r1
ad_cal1:
	mov temp2,mem_l
	mov temp1,mem_h
	lsl mem_l
	rol mem_h  ;x2
	swap temp1
	andi temp1,0xf0
	add mem_h,temp1
	swap temp2
	mov temp1,temp2
	andi temp1,0x0f
	andi temp2,0xf0
	add mem_l,temp2
	adc mem_h,temp1 ;x2 + x16=  x18
	ret
;**********************************************
start_c:
	sbi	PORTC,scl
	ldi	temp1,2
	rcall	wait_us
	cbi	PORTC,sda
	ldi	temp1,3
	rcall	wait_us
	ret
stop_c:
	cbi	PORTC,scl
	ldi	temp1,2
	rcall	wait_us
	cbi	PORTC,sda
	ldi	temp1,2
	rcall	wait_us
	sbi	PORTC,scl
	ldi	temp1,5
	rcall	wait_us
	sbi	PORTC,sda
	ret

send_dat_re:	;re_start
	ser r21
	rjmp s_d0
send_dat:
	clr r21
s_d0:
	ldi	temp4,8
s_d1:
	cbi	PORTC,scl
	ldi	temp1,1
	rcall	wait_us	
	lsl	temp3
	brcs	s_d2
	cbi	PORTC,sda
	rjmp	s_d3
s_d2:
	sbi	PORTC,sda
s_d3:
	ldi	temp1,1
	rcall	wait_us
	sbi	PORTC,scl
	ldi	temp1,4
	rcall	wait_us	
	dec	temp4
	brne	s_d1
s_d4:
	cbi	PORTC,scl
	nop
	cbi	DDRC,sda	;input
	ldi	temp1,3
	rcall	wait_us
	tst r21
	brne s_d5
	cbi	PORTC,sda
	rjmp s_d6
s_d5:
	sbi	PORTC,scl
	ldi	temp1,4
	rcall	wait_us
	cbi	PORTC,scl
	sbi	PORTC,sda
	sbi	DDRC,sda	;output
	ldi	temp1,3
	rcall	wait_us
	ret
s_d6:
	sbi	DDRC,sda	;output
	sbi	PORTC,scl
	ldi	temp1,3
	rcall	wait_us
	ret

read_last_dat:
	ser r21
read_dat:
	ldi	temp4,8
	clr temp3
r_d1:
	cbi	PORTC,scl
	ldi	temp1,4
	rcall	wait_us
	cbi	DDRC,sda	;input	
	sbi	PORTC,scl
	ldi	temp1,2
	rcall	wait_us
	clc
	sbic PINC,sda
	sec
	rol	temp3
	ldi	temp1,1
	rcall	wait_us
	dec	temp4
	brne	r_d1
	cbi	PORTC,scl
	ldi	temp1,1
	rcall	wait_us
	cbi	PORTC,sda   ;ACK
	sbi	DDRC,sda	;output
	tst r21
	breq r_d2
	sbi	PORTC,sda	;last data >> NACK send
r_d2:
	ldi	temp1,2
	rcall	wait_us
	sbi	PORTC,scl
	ldi	temp1,3
	rcall	wait_us
	ret

mem_r0:
	ldi r20,2-1
	rjmp mem_r1
mem_r:
	ldi r20,18-1
mem_r1:
	clr r21
	ldiw z,kp_dat
	rcall mem_w
	mov temp3,mem_h
	rcall	send_dat
	mov temp3,mem_l
	rcall	send_dat_re	
	rcall	start_c	;re_start
	ldi	temp3,0b10100001	;SLA_R
	or temp3,mem_p0
	rcall	send_dat
mem_r2:
	rcall	read_dat
	st	z+,temp3
	dec r20
	brne mem_r2
	rcall	read_last_dat	;last data read,NACK send
	st	z+,temp3
	rcall	stop_c
	ret

mem_w:
	rcall	start_c
	ldi	temp3,0b10100000	;SLA_W
	or temp3,mem_p0
	rcall	send_dat
	ret

;**********************************************
lcd_int:
	cbi	PORTB,lcd_cs
	cbi	PORTB,lcd_rs
	ldi temp1,0xae	;display off
	rcall	spi_out
	ldi temp1,0xAE //Display = OFF
	rcall	spi_out
	ldi temp1,0xA0 //ADC = normal
	rcall	spi_out
	ldi temp1,0xC8 //Common output = revers
	rcall	spi_out
	ldi temp1,0xA3 //bias = 1/7
	rcall	spi_out
	//--内部レギュレータを順番にＯＮする--//
	ldi temp1,0x2C //power control 1
	rcall	spi_out
	ldi temp1,2
	rcall wait_ms
	ldi temp1,0x2E //power control 2
	rcall	spi_out
	ldi temp1,2
	rcall wait_ms
	ldi temp1,0x2F //power control 3
	rcall	spi_out
	//--コントラスト設定--//
	ldi temp1,0x23 //Vo voltage resistor ratio set
	rcall	spi_out
	ldi temp1,0x81 //Electronic volume mode set
	rcall	spi_out
	ldi temp1,0x1C //Electronic volume value set
	rcall	spi_out
	//--表示設定--//
	ldi temp1,0xA4 //display all point = normal（全点灯しない）
	rcall	spi_out
	ldi temp1,0x40 //display start line = 0
	rcall	spi_out
	ldi temp1,0xA6 //Display normal/revers = normal(白黒反転しない）
	rcall	spi_out
	ldi temp1,0xAF //Display = ON
	rcall	spi_out

	//Display clear
	ldi	temp2,0xb7//page address 7
dc0:
	mov	temp1,temp2
	cbi	PORTB,lcd_rs
	rcall	spi_out
	ldi temp1,0x10 //column address 0
	rcall	spi_out
	ldi temp1,0x00 //column address 0
	rcall	spi_out
	ldi	temp3,128
	sbi	PORTB,lcd_rs
	clr	temp1
dc1:
	rcall spi_out
	dec temp3
	brne dc1
	dec	temp2
	cpi temp2,0xb0
	brpl dc0
	sbi	PORTB,lcd_cs
	ret
;**********************************************
;lcd_com:
;	cbi	PORTB,lcd_rs
;	rjmp	lcd_dsp1
;lcd_dsp:
;	sbi	PORTB,lcd_rs
;lcd_dsp1:
;	cbi	PORTB,lcd_cs
;	rcall spi_out
;	sbi	PORTB,lcd_cs
;	ret

;**********************************************
;SPI DATA output   data=temp1
spi_out:
	out	SPDR,temp1
spi_out1:
	in	r15,SPSR
	sbrs	r15,SPIF
	rjmp	spi_out1
	ret
;*********************************************
Tx:
	LDS	r0,UCSR0A
	SBRS r0,UDRE0	;送信ﾊﾞｯﾌｧ空きでｽｷｯﾌﾟ
	RJMP Tx 		;送信ﾊﾞｯﾌｧ空き待機
	STS UDR0,R16	;ﾃﾞｰﾀ送信(送信開始)
	RET 			;呼び出し元へ復帰
Rx:
	LDS	r0,UCSR0A
	SBRS r0,RXC0	;受信完了でｽｷｯﾌﾟ
	RJMP Rx 		;受信完了待機
	LDS R16,UDR0	;受信ﾃﾞｰﾀ取得
	RET				;呼び出し元へ復帰
;**********************************************
wait_us:	;base 8MHz  temp1　us (4clocks)
	nop			; 1clocks			
	dec	temp1		; 1clocks
	brne	wait_us		; 2clocks
	ret			; 
wait_ms:	;temp1　ms
	ldi	temp2,100	;80*100=8000clocks
wait_ms_01:
	ldi	temp3,19    	;1clocks  4*(19+1)=80
wait_ms_02:
	nop			; 1clocks
	dec	temp3		; 1clocks
	brne	wait_ms_02	; 2clocks
	dec	temp2		; 1clocks
	brne	wait_ms_01	; 2clocks
	dec	temp1		; 1clocks	
	brne	wait_ms		; 2clocks
	ret
;*********************************************